(1) Field of the Invention
The invention relates to the fabrication of integrated circuit devices, and more particularly, to a method of forming ultra-shallow junctions for PMOSFETs in the fabrication of integrated circuits.
(2) Description of the Prior Art
The major constraint for sub-0.25 xcexcm technology integrated circuits is short channel effect (SCE). As device sizes decrease, the channel length decreases. Usually, as the channel length is reduced, the threshold voltage decreases. If the threshold voltage drops below its designed value, the device may exhibit excessive drain leakage current. Shallow junctions can contain the short channel effect. However, shallow junctions are more difficult to achieve for PMOS than for NMOS because boron diffuses much faster than arsenic and exhibits severe transient enhanced diffusion (TED). Rapid thermal annealing (RTA) has been proposed to reduce TED in order to achieve shallow junctions. Now, it is commonly accepted to perform an RTA prior to spacer deposition for 0.25 xcexcm and beyond technology. However, ultra-shallow junctions, less than about 20 to 60 nanometers in depth, cannot be achieved even with this method. It is desired to find a method to fabricate ultra-shallow junctions with improved short channel effect control and without side effects such as reverse short channel effect.
U.S. Pat. No. 5,985,726 to Yu et al teaches the formation of ultra-shallow junctions using dummy gates and LDD and pocket implant processes. U.S. Pat. No. 5,923,969 to Oyamatsu teaches a controlled pocket implant and LDD process using dummy gate. U.S. Pat. Nos. 5,757,045 and 5,668,024 to Tsai et al disclose the formation of pocket implants, LDD, and source/drain extensions followed by RTA. This method could present a problem in forming ultra-shallow junctions. U.S. Pat. No. 5,409,848 to Han et al teaches an angled pocket implant followed by RTA. U.S. Pat. No. 5,185,280 to Houston et al teaches a process including a halo implant.
A principal object of the present invention is to provide an effective and very manufacturable method of forming ultra-shallow junctions in the fabrication of integrated circuits.
A further object of the invention is to provide a method of forming ultra-shallow junctions while controlling short channel effects.
Another object of the invention is to provide a method of forming ultra-shallow junctions for PMOSFET while controlling short channel effects.
Yet another object is to provide a method of forming ultra-shallow junctions while controlling short channel effects and avoiding side effects such as reverse short channel effects.
Yet another object is to provide a method of forming ultra-shallow junctions while controlling short channel effects wherein a RTA is performed prior to the PLDD implant.
In accordance with the objects of this invention a method for forming ultra-shallow junctions for PMOSFET while reducing short channel effects is achieved. A semiconductor substrate wafer is provided wherein there is at least one NMOS active area and at least one PMOS active area. Gate electrodes are formed in both the NMOS and PMOS areas. N-type source/drain extensions are implanted into the NMOS area. The wafer is annealed whereby the n-type source/drain extensions are driven in. Thereafter, p-type source/drain extensions are implanted in the PMOS area wherein the p-type source/drain implants are not subjected to an annealing step. Spacers are formed on sidewalls of the NMOS and PMOS gate electrodes. Source/drain regions are implanted into the NMOS and PMOS areas wherein the source/drain regions are self-aligned to the spacers to complete formation of an integrated circuit device.